A 2-bit comparator compares two 2-bit words, A and B, and assets outputs indicating whether the decimal equivalent of word A is less than, greater than or equal to that of word B. K-map method can be used to derive the minimized equations to describe the behavior of the comparator and Verilog module can be written to test the working of the comparator. Complete the following:

Derive minimized equations for the comparator outputs - A less than B, A equal to B, and A greater than B. Done

Draw logic diagram. done

Write and test the Verilog Module for this comparator.