a) A Moore sequential circuit has two inputs (X and Y) and three outputs (Z2, Z, and Zo). The outputs are a 2's complement number specifying the number of successive times X and Y have been equal or not equal as follows: In decimal, the outputs are 1, 2, and 3 if X and Y have been equal for one time, two successive times, and three or more successive times, and the outputs are -1, -2, -3, and -4 if X and Y have been not equal for one time, two successive times, three successive times, and four or more successive times. Initially, the outputs are all 0. Construct a state diagram for the circuit and realize it using D flip-flops and minimum number logic gates. Assume X as MSB and Y as LSB, Z as MSB and Zo as LSB. Use straight binary state assignment. b) Design a 4:1 MUX only using minimum number of 2:1 MUXS.