a$.$ An implementation using a $4-$to$-16,$ active high output, decoder has the decoder outputs, $1\mathrm{.}6\mathrm{.}7\mathrm{.}10,12,13,14,15$ linked with an OR gate and the decoder inputis ABCD, where A represents the most signifcant bitb.An implementation using a $4-10-16,$ active high output, decoder has the decoder outputs, $1\mathrm{.}6\mathrm{.}7\mathrm{.}10,12,13,14,15$ linked with a NAND gate and the decoder input is ABCD, where A represents the most signticant bitc. The output can be wrtten as F $=$ ABCD$+$ABCD$-$AB CD $+$ABd. Al of the above are livee. None of the above are truef. a$)$ and c$)$ are both true$8.$ Only a$)$ is true