$($a$)$ Assuming a cache of data size $512$ KiB blocks, a $64$ byte block size, and a $64-$bit address, find the total number of tag bits and the cache size if the cache is a$)$ direct mapped b$)$ Eight way associative.

$($b$)$ Consider a processor with following data:

$\backslash$table$[[\backslash$table$[[$Base$],[$CPI$,$ No$],[$Memory$],[$Stalls$]],\backslash$table$[[$Processor$],[$Speed$]],\backslash$table$[[$Main$],[$Memory$],[$Access$],[$Time$]],\backslash$table$[[$First Level$],[$Cache$],[$MissRate$],[$per$],[$Instruction$]],\backslash$table$[[$Second$],[$Level$],[$Cache$,],[$Direct$-],[$Mapped$],[$Speed$]],\backslash$table$[[$Local$],[$Miss$],[$Rate$],[$with$],[$Second$],[$Level$],[$Cache$,],[$Direct$-],[$Mapped$]],\backslash$table$[[$Second$],[$Level$],[$Cache$.],[$Eight$-$Way$],[$Set$],[$Asoociative$],[$Speed$]],\backslash$table$[[$Loeal$],[$Miss Rate$],[$with$],[$Second$],[$Level$],[$Cache;$],[$Eight$-$Way$],[$Set$],[$Assoxiative$]]],[1\mathrm{.}5,3GHz,150ns,8\%,\backslash$table$[[15],[$cycles$]],30\%,25$ cycles,$20\%$