A benchmark in a 5-stage pipelined processor that uses a Branch Target Buffer (BTB) has the following characteristics: Problem l.1 i a 5:astage pipelined processor that [35 points] 23% ALU instructions, 26% Load instructions 33% of instructions are followed by another instruction that needs the data 28% are branch instructions that need data to determine branch condition. 12% are store instructions that write data being loaded to memory-different address 11% 26% 14% Store instructions Branch instructions (62% of these branches are taken). Jump instructions The branch-target buffer (BTB) for conditional branch and jump instructions has the following features. Jump 83% 64% Comment Feature Bh Hit Rate 89% Accuracy 85% This is the number of times the address (PC) is found in the BTB This is the number of times the prediction is correct/right If a branch is not found in BTB the default prediction is not taken. Target addresses for both branch and jump instructions are known at the end of the ID stage a) Please determine the CPI (cycles per instruction). Please use CPI CPlideal +Stalls 23%| ALU 26%| Load A benchmark in a 5-stage pipelined processor that uses a Branch Target Buffer (BTB) has the following characteristics: Problem l.1 i a 5:astage pipelined processor that [35 points] 23% ALU instructions, 26% Load instructions 33% of instructions are followed by another instruction that needs the data 28% are branch instructions that need data to determine branch condition. 12% are store instructions that write data being loaded to memory-different address 11% 26% 14% Store instructions Branch instructions (62% of these branches are taken). Jump instructions The branch-target buffer (BTB) for conditional branch and jump instructions has the following features. Jump 83% 64% Comment Feature Bh Hit Rate 89% Accuracy 85% This is the number of times the address (PC) is found in the BTB This is the number of times the prediction is correct/right If a branch is not found in BTB the default prediction is not taken. Target addresses for both branch and jump instructions are known at the end of the ID stage a) Please determine the CPI (cycles per instruction). Please use CPI CPlideal +Stalls 23%| ALU 26%| Load