A clocked Mealy sequential network has one input and one output. The network

output is to be $Z=1,$ if the total number of logic$-0\text{'}$s received is even number greater

than zero, and the total number of logic$-1\text{'}$s recieved is odd number, provided that two

consecutive logic$-1\text{'}$s have never been recieved. Give state graph includes minimum states.

Design this circuit by using minimum number of JK FF and logic gates. $($Note: Write the

output equation of the network and the input equations for one of the JK FF$.)(35$ marks$)$