A company has designed a new $9-$stage instruction pipeline processor:

IF $->$ ID $->$ RF $->$ Q$1->$ Q$2->$ Q$3->$ M$1->$ M$2->$ WB

In this architecture, IF is for instruction fetch, ID is for instruction decoding, RF is for register file read, Q$1$

Q$2$ and Q$3$ are for ALU execution, M$1$ and M$2$ are for memory access, and WB is for write back. Assume

that the branch target address is calculated at stage Q$1,$ and the outcome of the branch condition is

determined at stage Q$3.$ All ALU instructions go through Q$1,$ Q$2$ and Q$3$ stages and all memory

instructions go through M$1$ and M$2$ stages.