A CPU is connected to DRAM via a $128-$bit bus. It takes one bus cycle for address transfer, $2$ bus cycles for data transfer, and $8$ bus cycles for the DRAM to access one word. There are $8$ banks in the DRAM, and the banks can be accessed in parallel. Assume data transfer over the bus does not overlap with DRAM access.

In order for the CPU to read $51$ consecutive words from the DRAM,

How many bus cycles are needed for DRAM access?

How many bus cycles are needed in total to complete the read?

In order for the CPU to read $51$ scattered words from the DRAM, how many bus cycles are needed in total to complete the read?