$($a$)$ Design and implement a memory control logic circuit using the minimum number of suitable size decoder$($s$)$ and logic gates. The circuit must generate ten $($Q$0---$ Q$9)$ active low outputs $($enable signals$)$ depending on five inputs shown in the truth Table $3.$

$(12$ marks$)$

Table $3$

$\backslash$table$[[$Inputs$,$Output$],[$Select$,$Read$-$Mem,I$\_(2),$I$\_(1),$I$0,],[1,$x$,$x$,$x$,$x$,$none$],[$x$,1,$x$,$x$,$x$,$none$],[0,0,0,0,0,$Q$0,$ Q$8],[0,0,0,0,1,$Q$3,$ Q$5],[0,0,0,1,0,$Q$4],[0,0,0,1,1,$Q$6],[0,0,1,0,0,$Q$7],[0,0,1,0,1,$Q$2],[0,0,1,1,0,$Q$9],[0,0,1,1,1,$Q$1]]$