A design is given with its RTL code, synthesis netlist, and layout $($vias for cell pins are ignored

for simplicity$)$ as below.

$(2$pt$)$ There is an error of wire connection in the layout. Indicate where it is$,$ e$.$g$.$ simply

mention the connection of $u{0}_a.$out and $u{0}_{?}$and$\_0.$in$\_0.$

$(2$pt$)$ Describe how to automatically detect such errors using EDA tools?

$(2$pt$)$ What connection should be established instead?

$(8$pt$)$ Unfortunately, the careless designer also finds out that the specification for the register

$d$ should be $"dd+b+a$;$",$ not $"dd+b$;$",$ and the backend team tells her that there

are no spare cells available. Please help this desperate designer. Indicate how we should

proceed ECO by modifying the netlist and the layout.

$(2$pt$)$ Describe how to confirm the correctness of such ECO using EDA tools.