A dual processor SMP system includes an L1 data cache for each processor and employs the MESI protocol to maintain cache consistency. Each cache is a 2-way set associative copy-back cache that contains a total of 8192 cache lines each of which is 256 bytes in size. Way0 within each empty set is filled first. A write-allocate policy is used for each cache. One process, P1, runs on the first processor at the same time that another process, P2, runs on the other processor. P1 reads a variable X with an initial value of 80 that resides in memory at address 0x400804C0. After P1 reads X, P2 writes the value 156 into a variable Y with an initial value of 200 that resides in memory at address 0x400804F8. All caches are initially empty. That is, initially all cache lines have a MESI state of I (invalid).

a) What is the final MESI state of the line containing X in P1s cache and how is P2s cache affected when P1 reads X?

b) What is the final MESI state of the line containing Y in P2s cache and how is P1s cache affected when P2 writes Y?