A flip-flop is in the HIGH state when Q = 1.

True

False

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Question 81 pts

A small triangle at the CLK input on a standard flip-flop symbol indicates that any change in the output is triggered by a clock transition.

True

False

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Question 91 pts

Synchronous (parallel) counters do not experience the delay problems encountered with asynchronous (ripple) counters because:

the input clock pulses are applied only to the last stage.

the input clock pulses are applied simultaneously to each stage.

the input clock pulses are applied only to the first and last stage.

the input clock pulses are not used to activate any of the counter stages.

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Question 101 pts

A production plant needs a counter that will count 4,000 items before resetting and recycling. How many flip-flop stages would this counter require?

10

12

13

11

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Question 111 pts

What type of register accepts data inputs one bit at a time and outputs all its data bits at the same time?

Parallel in/Serial out

Serial in/Parallel out

Serial in/Serial out

Parallel in/Parallel out

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Question 121 pts

A parallel in/parallel out register normally has data inputs loaded ________ and data outputs transferred ________.

asynchronously, asynchronously

asynchronously, synchronously

synchronously, asynchronously

synchronously, synchronously