A flip-flop is in the HIGH state when Q = 1.

True

False

Flag this Question

Question 81 pts

A small triangle at the CLK input on a standard flip-flop symbol indicates that any change in the output is triggered by a clock transition.

True

False

Flag this Question

Question 91 pts

Synchronous (parallel) counters do not experience the delay problems encountered with asynchronous (ripple) counters because:

the input clock pulses are applied only to the last stage.

the input clock pulses are applied simultaneously to each stage.

the input clock pulses are applied only to the first and last stage.

the input clock pulses are not used to activate any of the counter stages.

Flag this Question

Question 101 pts

A production plant needs a counter that will count 4,000 items before resetting and recycling. How many flip-flop stages would this counter require?

10

12

13

11

Flag this Question

Question 111 pts

What type of register accepts data inputs one bit at a time and outputs all its data bits at the same time?

Parallel in/Serial out

Serial in/Parallel out

Serial in/Serial out

Parallel in/Parallel out

Flag this Question

Question 121 pts

A parallel in/parallel out register normally has data inputs loaded ________ and data outputs transferred ________.

asynchronously, asynchronously

asynchronously, synchronously

synchronously, asynchronously

synchronously, synchronously

Flag this Question

Question 131 pts

The type of counter where each flip-flop provides the CLK input to the next flip-flop is referred to as a ________ counter.

Synchronous

Ripple

Parallel

Quadratic

Flag this Question

Question 141 pts

All decade counters are BCD counters.

True

False