A microprocessor has a decrement memory direct instruction, which subtracts one from the value in a memory location. The instruction has five stages: fetch opcode $($four bus clock cycles$),$ fetch operand address $(5$ bus clock cycles$),$ fetch operand $($five bus clock cycles$),$ Subtract $1$ from operand $($five bus clock cycles$),$ and store operand $(6$ bus clock cycles$).$ Marks

a$.$ By what amount $($in percent$)$ will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation?

b$.$ Repeat assuming that the decrement operation takes $10$ cycles instead of $5$ cycles