6. A microprocessor has an increment memory direct instruction, which adds 1 to the value in memory location. The instruction has five stages: fetch opcode (four bus clock cycles); fetch operand address (four bus clock cycles); fetch operand (five bus clock cycles); add 1 to operand (three bus clock cycles); and, store operand (two bus clock cycles). By What amount (in percent) will the duration of the instruction increase if we have to insert four bus wait states in each memory read and memory write operation?