A microprocessor has a decrement memory direct instruction, which Subtracts one from the value in a memory location. The instruction have five stages: fetch opcode $($fiver bus Clock Cycles$),$ fetch operand address $($four bus clock cycle$),$ fetch operand $($three bus clock cycles$),$ Subtract one from Operand $($three bus clock Cycler$),$ and store Operand $($five bus Clock Cycles$).$

a$.$ By what amt $($in$\%)$ will the duration of the instruction icrease if we have to insert two bus wait States each memory read & memory write Operation

b$.$ Repeat assuming that the decrement Operation takes $10$ Cycles, instead of$5.$ Cycles