A MIPS processor has a 32-bit address bus with and a cache memory to hold 8K (=2^13) memory words. If a 4-way set associated cache is used to implement cache with a block size of 8 main memory words then find:

· Number of bits for block field

· Number of bits for set field

· Number of its for-tag field

· The capacity in number of main memory words

· Actual size of the cache memory with a valid bit for each set V.

Answer rating: 100% (QA)

To determine the number of bits required for the block field set field tag field cache capacity and ... View the full answer