Question: A MIPS processor has a 32-bit address bus with and a cache memory to hold 8K (=2^13) memory words. If a 4-way set associated cache

A MIPS processor has a 32-bit address bus with and a cache memory to hold 8K (=2^13) memory words. If a 4-way set associated cache is used to implement cache with a block size of 8 main memory words then find:

· Number of bits for block field

· Number of bits for set field

· Number of its for-tag field

· The capacity in number of main memory words

· Actual size of the cache memory with a valid bit for each set V.

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