A pipelined processor has a clock rate of $2\mathrm{.}5$ GHz and executes a program with $1\mathrm{.}5$ mil$-$ lion instructions. The pipeline has five stages, and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instructions and out$-$of$-$sequence executions.

a$.$ What is the speedup of this processor for this program compared to a nonpipe$-$ lined processor, making the same assumptions used in Section $14\mathrm{.}4?$

b$.$ What is throughput $($in MIPS$)$ of the pipelined processor?