A processor has separate instruction and data caches, each requiring two cycles for any operation. It includes a single 2-cycles execution unit responsible for executing all ALU and LOAD instructions. As a result, the instruction pipeline has the following eight stages: IF1, IF2, ID, EX1, EX2, MEM1, MEM2, WB. In the absence of hazards the pipeline has a CPI of 1. The processor has no hardware support for dynamic scheduling. The instruction stream executed by the processor consists of 25% Load instructions and 40% ALU instructions. The frequencies of RAW data dependencies between these two instructions and the instructions following them are:

a) Calculate the contribution to the CPI of the processor due to RAW data hazards assuming that NO DATA FORWARDING IS SUPPORTED. Note that the Register File can execute a write followed by a read in the same cycle. Contribution to CPI =____?

(b) Calculate the contribution to the CPI of the processor due to RAW data hazards assuming that DATA FORWARDING IS SUPPORTED. Note that the Register File can execute a write followed by a read in the same cycle. Contribution to CPI =____?

LOAD ALU Instruction i RAW in instructioni+ 1 30% 20% RAW in instruction i+2, but not in i+ 1 12% 10% RAW in instruction i+3, but neither in i+1 nor in i+2 10% 5% RAW in instruction i 4, but not in an earlier one 5% 196 LOAD ALU Instruction i RAW in instructioni+ 1 30% 20% RAW in instruction i+2, but not in i+ 1 12% 10% RAW in instruction i+3, but neither in i+1 nor in i+2 10% 5% RAW in instruction i 4, but not in an earlier one 5% 196