Question: A processor takes one clock cycle to execute each instruction, when no memory stalls are present. Its level 1 cache has a miss rate

A processor takes one clock cycle to execute each instruction, when no memory stalls are present. Its level 1 cache has a miss rate of MR% while the level 2 cache has a miss rate MR% and access time of CC clock cycles. Main memory takes CC clock cycles to be accessed. The CPI taking into account the memory stall cycles, assuming MAPI accesses to memory per instruction is

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