A program is executed on this CPU with base CPI of $2$ cycles and cache miss penalty of $90$ cycles. It is measured that the I$-$cache miss rate is $0\mathrm{.}04,$ and the D$-$cache miss rate is $0\mathrm{.}03.$ In addition, $20\%$ of the instructions executed are load instructions and $20\%$ are store. The write policy of the D$-$cache is write$-$back. Assume the cache is always full. The probability of a replaced D$-$cache block being dirty is $0\mathrm{.}15.($Note that no I$-$cache block is dirty.$)$