A program is executed on this CPU with base CPI of $1$ cycles and cache miss penalty of $70$ cycles. It is measured that the I$-$cache miss rate is $0\mathrm{.}02,$ and the D$-$cache miss rate is $0\mathrm{.}05.$ In addition, $10\%$ of the instructions executed are load instructions and $20\%$ are store. The write policy of the D$-$cache is write$-$back. Assume the cache is always full. The probability of a replaced D$-$cache block being dirty is $0\mathrm{.}07.($Note that no I$-$cache block is dirty.$)$

What is the average miss penalty for a data cache miss?

What is the average CPI for instructions that are neither load nor store?

What is the average CPI for load and store instructions?

What is the average CPI for all instructions?

Round the answers to the nearest hundredth and separate them with commas. Make sure there are two decimal places in each answer even if both are zero. For example, if the answer is $1,$ it should be written as $1\mathrm{.}00.$

This should be the correct answer: $74\mathrm{.}90,2\mathrm{.}40,6\mathrm{.}15,3\mathrm{.}52$ please show calculations