A RISC based CPU is to be designed to have $32$ instructions, source and destination operands referring to $64$ registers, and a displacement of value such as $2$ABCH. For example: ADD R$1,$ R$2.2$ABCH, where ADD is the opcode, R$1$ is source as well as destination register, R$2$ is the base register, and $2$ABCH is the displacement that gets added to base register to generate effective address of the data. Present the instruction format specifying various fields and bits required by them.