. A sequential circuit has one input (X) and two outputs (S and V). X represents a 4-bit binary number N, which is input least significant bit first. S represents a 4-bit binary number equal number equal to N+2, which is output least significant bit first. At the time the fourth input occurs, V-l if N+2 is too large to be represented by 4 bits; otherwise, V-0. The value of S should be the proper value, not a don't care, in both cases. The circuit always resets after the fourth bit of X has been received. The Mealy state graph is shown below. 0/00,1/10 S2 S3 0n So 0/10 1/00 S4 0/10,1/01 Write a behavioral Verilog description of the state machine. Assume that state changes occur on the falling edge of the clock pulse. Use a case statement together with if-then-else statements to represent the state table. . A sequential circuit has one input (X) and two outputs (S and V). X represents a 4-bit binary number N, which is input least significant bit first. S represents a 4-bit binary number equal number equal to N+2, which is output least significant bit first. At the time the fourth input occurs, V-l if N+2 is too large to be represented by 4 bits; otherwise, V-0. The value of S should be the proper value, not a don't care, in both cases. The circuit always resets after the fourth bit of X has been received. The Mealy state graph is shown below. 0/00,1/10 S2 S3 0n So 0/10 1/00 S4 0/10,1/01 Write a behavioral Verilog description of the state machine. Assume that state changes occur on the falling edge of the clock pulse. Use a case statement together with if-then-else statements to represent the state table