A sequential circuit is required that can generate an even parity for a

sequence of $5-$bit binary data. The $5-$bit binary number is available on a

serial input channel. The even$-$parity generator circuit receives a serial

stream of $5-$bit number, start Synch pulse and a synchronizing clock from

a data system as shown in Figure Q$5.$ The parity generator circuit asserts

its even parity output $($even$)$ for one clock cycle, when it receives the $5-$

bit number starting with a Synch pulse of one clock cycle duration at the

positive transitions of the Clock. The main features of the system are

given below:

Clock signal from the data system unit shifts the data bits in serially.

Each input bit spans between consecutive negative transitions of the

clock.

The $5-$bit serial data starts with its least significant bit.

Design the Parity generator circuit such that its output, even is available

during the $5$th bit of a $5-$bit data. The even parity bit is set or reset to

have an even number of $1\text{'}$s in the $6-$bit number $(5-$bit Data and $1-$bit

parity$).$

$($a$)$ Draw the state diagram and state table for the even$-$parity

generator sequential circuit.

$(7$ marks$)$

$($b$)$ Design the parity generator by using a suitable edge$-$triggered

$($negative or positive$)$ D$-$type flip$-$flops.

$(12$ marks$)$

$($c$)$ Implement and draw the circuit diagram of the parity generator

designed in part $($b$)$ showing all the details.

$(6$ marks$)$