A synchronous digital logic system has one input, X, and two outputs, Y and Z. The system samples input line X on the rising edge of the clock and (1) sets the output Y to "1" whenever the system has detected two consecutive sample values of X to be "1" and (2) sets the output Z to "1" whenever the system has detected two consecutive sample values of X to be "0". In cases other than (1), Y is "0", and, in cases other than (2), Z is "0". Draw the state diagram for a Moore state machine for the system using transition expressions on the transition arcs. Indicate the meaning of each state.