Question: A synchronous digital logic system has three inputs, W, X and Y, and one output, Z. The system samples input lines X and Y on

A synchronous digital logic system has three inputs, W, X and Y, and one output, Z. The system samples input lines X and Y on the rising edge of the clock and sets the output Z to "1" whenever the system has detected X and Y to be different for two consecutive samples and the current value of input W is "1". Otherwise, output Z is set to "0". Draw the state diagram for a Mealy state machine for the system using transition expressions on the transition arcs. Assume that your state machine starts in state "A".

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