A system contains 8 registers, each of which is 16 bits wide. Outputs of all registers...

Transcribed Image Text:

A system contains 8 registers, each of which is 16 bits wide. Outputs of all registers are connected to a common 16 bit bus through tri-stateable drivers. A 3 to 8 decoder pro- vides negative true RegSel; outputs, which are used to enable one out of the 8 registers to place its contents on the bus. Each RegSel, line from the decoder drives a fork whose branches contain 2 and 3 inverters to provide Enable and Enable signals, which in turn drive the p and n channel transistors of the 16 tristateable drivers for all the bits of the selected register i. RegSel From Reg. The total load presented by the two arms of the fork Decoder on the Selį line should be equivalent to 4 minimum inverters. Each tri-stateable driver should provide a drive strength equivalent to 3 minimum inverters. To 15 other bits of this register Enable Reg-bit in o Enable To 15 other bits of this register Von Tri-statable Bit driver Reg-bit out For all parts of this question, assume that the parasitic delay of an inverter is 1.55, and p channel transistors should be twice as wide as n channel transistors to provide the same drive current (y = 2). a) What is the difference between stage effort values represented by f and p? Find the optimum stage effort p for inverter parasitic delay Pinv = 1.55. Use Newton Raphson iterations to solve the equation: p(ln p-1)- Pinv = 0 with a starting guess of 3.0. b) Find the size of the first inverters in the two branches of the fork such that the delay through the two branches is equal and the total load on the Selį line is equivalent to 4 minimum inverters. c) What is the total delay through either branch of the fork? d) Find the width of all transistors in the circuit shown above, in units of the width of the n channel transistor in the minimum inverter. Label all components and present your results in a tabular form. A system contains 8 registers, each of which is 16 bits wide. Outputs of all registers are connected to a common 16 bit bus through tri-stateable drivers. A 3 to 8 decoder pro- vides negative true RegSel; outputs, which are used to enable one out of the 8 registers to place its contents on the bus. Each RegSel, line from the decoder drives a fork whose branches contain 2 and 3 inverters to provide Enable and Enable signals, which in turn drive the p and n channel transistors of the 16 tristateable drivers for all the bits of the selected register i. RegSel From Reg. The total load presented by the two arms of the fork Decoder on the Selį line should be equivalent to 4 minimum inverters. Each tri-stateable driver should provide a drive strength equivalent to 3 minimum inverters. To 15 other bits of this register Enable Reg-bit in o Enable To 15 other bits of this register Von Tri-statable Bit driver Reg-bit out For all parts of this question, assume that the parasitic delay of an inverter is 1.55, and p channel transistors should be twice as wide as n channel transistors to provide the same drive current (y = 2). a) What is the difference between stage effort values represented by f and p? Find the optimum stage effort p for inverter parasitic delay Pinv = 1.55. Use Newton Raphson iterations to solve the equation: p(ln p-1)- Pinv = 0 with a starting guess of 3.0. b) Find the size of the first inverters in the two branches of the fork such that the delay through the two branches is equal and the total load on the Selį line is equivalent to 4 minimum inverters. c) What is the total delay through either branch of the fork? d) Find the width of all transistors in the circuit shown above, in units of the width of the n channel transistor in the minimum inverter. Label all components and present your results in a tabular form.

Answer rating: 100% (QA)

The detailed ... View the full answer