a) The activity shown in Table Q1 (a) are processes carried out in a semiconductor company. Based on the table provided, (1) Determine the Critical Path and Project Duration to complete the process using a Network Diagram. Activity D cannot start immediately after activity A. The delay is expected to be 7 days. Determine by stating the possible problem, Critical Path and Project Duration to complete the process. Table Q1 (a) Activity Process Predecessor A B D E F G H I J K L M Wafer Processing Dry etching Wet etching Plasma aching Thermal treatment Chemical vapor deposition Electrochemical deposition Wafer testing Die preparation IC bonding IC plating IC testing IC packaging A B A D, B, C F EF G H I K J.L Duration (Days) 2 1 3 2 4 1 3 4 2 5 3 2 1