A very simple algorithm to compute the square root of a number is shown below. To simplify the problem, we assume that the number is a perfect square (e.g., 4, 9, 16, 25, .). There are three registers Rn, Rdelta, and Rdata in the data path to store the data. For example, to compute the square root of 25, 25 will be loaded into register Rdata from input port num. Rn is initialized to 1 and Rdelta is initialized to 3 as shown in iteration 1.

Iteration Rn Rdelta Rdata

1 1 3 25

2 4 5 25

3 9 7 25

4 16 9 25

5 25 11 25

Design specification.

Block diagram (modules and their relationship) of the entire lab.

Block diagram of the data path.

Verilog code (your behavioral level design) for the Data Path module.

State diagram of the Controller.

Testbench (you can copy of testbench given above) for the Data Path module, and the simulation waveform by the testbench.

Design Time (in hours) to complete the pre-lab phase of this task