Lets explore 2 different cache implementations that will determine the processor's performance CI: 1KB, Miss rate-796, Hit time-0.25 ns C2: 4KB, Miss rate = 3%. Hit time = 0.75 ns If the hit time defines the frequency of operation of the processor pipeline, what is the frequency of the processor if using the C1 cache implementation? (format is in GHz to 2 decimal places) If upon a miss, the instruction cache must be filled from main memory whose access time to fill the cache is 120 nS, what is the average memory access time for the C1 processor implementation due to accessing main memory? (format is in ns to two decimal places) Assuming a base CPl of 1.0 without memory stalls, and assuming both processors operate at the same clock frequency, which processor is higher performing? (Answer format, C1 or C2) If we add an L2 cache based on the following, what would be the average memory access time for the C1 implementation due to fetching data to fill the L1 cache? L2: 1MB, Hit Rate 92%, Hit time = 5.00ns (format is in nS to 2 decimal places) If the L2 cache was added to the C1 cache, how much faster would the L2 implementation be compared to no L2? (format, answer to two decimal places) Lets explore 2 different cache implementations that will determine the processor's performance CI: 1KB, Miss rate-796, Hit time-0.25 ns C2: 4KB, Miss rate = 3%. Hit time = 0.75 ns If the hit time defines the frequency of operation of the processor pipeline, what is the frequency of the processor if using the C1 cache implementation? (format is in GHz to 2 decimal places) If upon a miss, the instruction cache must be filled from main memory whose access time to fill the cache is 120 nS, what is the average memory access time for the C1 processor implementation due to accessing main memory? (format is in ns to two decimal places) Assuming a base CPl of 1.0 without memory stalls, and assuming both processors operate at the same clock frequency, which processor is higher performing? (Answer format, C1 or C2) If we add an L2 cache based on the following, what would be the average memory access time for the C1 implementation due to fetching data to fill the L1 cache? L2: 1MB, Hit Rate 92%, Hit time = 5.00ns (format is in nS to 2 decimal places) If the L2 cache was added to the C1 cache, how much faster would the L2 implementation be compared to no L2? (format, answer to two decimal places)