A window watchdog timer, like that in figure below$-$left, is a watchdog timer that

monitors if the signal from the processor fails to send before the watchdog timeout ends

$($i$.$e$.$ upper watchdog boundary$)$ and also if the processor sends the watchdog input $($WDI$)$

signal before the watchdog timeout window begins $($i$.$e$.$ lower watchdog boundary$).$

rarr This functionality is illustrated in figure below$-$right.

rarr In an embedded system with clock frequency of $10$ MHz $,$ use appropriate counters to

design a window watchdog with

a$.$ quad Upper Watching Boundary $=5$sec and Lower Watching Boundary $=1$min

b$.$ Upper Watching Boundary $=1$ms and Lower Watching Boundary $=10$sec WDI: Watchdog Input WDO: Watchdog Output

UWB: Upper Watching Boundary

LWB: Lower Watching Boundary