A) Write an 8:1 multiplexer module in Verilog, called mux8 with selection input s[2:0], data inputs d0, d1, d2, d3, d4, d5, d6, d7, and data output y. The bit width of all data inputs and outputs should be parameterized by width. Use case statement with behavioural model.

B)Write a structural module in Verilog to compute the logic function, y = ab + bc + abc, using multiplexer logic. Use the 8:1 multiplexer from A as the building block with structural model only