According to the MIPS pipelined processor characteristics, select the statement that is not correct:Group of answer choicesIn control hazard, if the branch condition $($in bne instruction$)$ is False, the processor would continue fetching the next instruction in sequential order $($PC$+4).$ The store and load instructions behave similarly in stage $2($instruction decode$).$The length of the clock cycle is sepecified by the sum of fastest stages of the pipeline. Branch target address is calculated in Execution stage of pipeline.