Add Ex ALU 4 - Addresult Shift left 2 RegDst Branch MemRead Instruction (31-26] MemtoReg Control ALUOP Mem Write ALUSrc RegWrite Instruction (2521] PC Read address Instruction (20-16] Read register 1 Read Read data 1 register 2 Write Read Zero ALU ALU Instruction [31-0] Instruction memory 0 M Instruction (1511] result Address Read data register data 2 Esx_ x=3 Write data Registers Write Data data memory Instruction (150] 16 32 Sign- extend ALU control Instruction [50] Consider the following instruction: AND Rd, Rs, Rt Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt]| = What are the values of the control signals generated by this control function? RegDst ALUOP Branch Mem Write MemRead ALUSrc WWW MemtoReg RegWrite wwwwwwwwwwww Which resources/blocks perform useful function for this instruction? Which resources/blocks produce outputs, but their outputs are not used for this instruction? Which produce no outputs