Algorithm Loops.

A Control Unit and Datapath are designed to act as a simple loop counter.

The Datapath contains a register that down$-$counts to zero.

The register transfers are

Load: Rlarrx$-1$

Dec: RlarrR$-1$

The Datapath produces a status signal called Zero that is true whenever the value of $R=0.$

The system has two states "idle" and "busy".

A $3-$bit input, X $,$ determines the number of cycles in which the system must occupy the "busy" state.

The control unit initiates the loop using two handshaking signals called "Start" and "Done".

The following two ASM charts describe control unit designs that implement different handshaking

protocols.

a$)$ Indicate beside the set of timing waveforms on the next page which set corresponds to Chart A and

which to set corresponds to Chart B$.$

b$)$ Predict the missing values of any incomplete signal waveforms. Algorithm Loops.

c$)$ Draw an ASM Chart for a Control Unit that implements the following protocol.

The Operand, X$,$ is guaranteed valid whenever Start $={?}^{\text{'}}1\text{'}.$

The counter, when busy, cannot be restarted until it has completed the correct number of "busy"

states.

The Done $=\text{'}1\text{'}$ whenever the system is idle.

The system may start a new loop immediately upon completing a previous loop without

becoming idle in between.