also after the code FA0 = there is ??? means that you should write thing

Complete the following VHDL code that implements a Three-Bit Parallel Adder by using structural modeling. Name your entity as ParallelAdder Assume fullAdder.vhd file is already defined. Note that you need to replace the questions marks with the suitable line of codes. 7 A B I 2 E Library IEEE; use IEEE.std_logic_1164.all; use work.all; entity parallelAdder is port ??? ); end parallelAdder; architecture struct of parallelAdder is component ??? end component; signal ??? begin FAO: fullAdder port map(AO), B(O), Cin, Coo, S(O))