Modeling and simulation of digital system . Using Vhdl

Design a package that includes the following components (You have also to write the code for each of these entities): - 2 x 4 Decoder - 4 x 1 Multiplexer -4 bit parallel adder. - 3 state buffer regular control Use this package to -Design a 16 bit parallel adder - Design a 16 x 1 multiplexer - Design a 5 x 32 decoder Design an inverted control sate buffer Write the code and run the simulation and in the submitted solution include the simulation results