An $8-$to$-1$ multiplexer is a digital device that selects one of the eight input lines to the output line by using three$-$bit selection lines. The block diagram of $8-$to$-1$ Mux is shown in Figure $1.$

$\backslash (0<mn>0</mn><mn>1</mn><mtext></mtext><mi>\backslash </mi><mi>)</mi>$ OU

Figure $1.$ Block diagram of $8-$to$-1$ multiplexer

Figure $2.$ Truth table of $8-$to$-1$ multiplexer

Multiplexer specifications:

$-8$ inputs $\backslash (\backslash$left$(\backslash$mathrm$\{$I$\}\_\{\backslash$mathrm$\{$i$\}\}\backslash$right$)\backslash )$ and $3$ select lines $\backslash (\backslash$left$($S$\_\{$i$\}\backslash$right$)\backslash ).$

$-$ True and complementary select inputs S$[2$:$0]$ are available.

$-$ Each select input $(\backslash ($ S$\_\{$i$\}\backslash ))$ may drive $10$ unit$-$sized transistors.

$-$ Each input $(\backslash (\backslash$mathrm$\{$I$\}\_\{\backslash$mathrm$\{$i$\}\}\backslash ))$ may drive $10$ unit$-$sized transistors.

$-$ The output $($Out$)$ bit presents load of $100$ unit$-$sized transistors.

For a faster $8-$to$-1$ multiplexer design you need to decide:

$-[1$ point$]$ How many stages to use?

$-[1$ point$]$ How large should each gate be$?$

$-[1$ point$]$ How fast can multiplexer operate?

Find the logic gate diagram using $($NAND$,$ NOR$)$ for the lowest Delay $($D$)$