An unpipelined processor takes 10 ns to work on one instruction. It then takes 0.2 ns to latch its results into latches. I was able to convert the circuits into 10 sequential pipeline stages. The stages have the following lengths: 1.3ns; 0.7ns; 0.8ns; 1.2ns;0.7ns; 1.4ns; 0.7ns; 0.4ns; 1.5ns; 1.3ns. Answer the following questions, assuming that there are no stalls in the pipeline. 1. What is the clock speed in the unpipelined and pipelined processors (in MHz)? 2. What are the IPCs in the unpipelined and pipelined processors? 3. How long does it take to finish one instruction in the unpipelined and pipelined processors (in nano-seconds)? 4. What is the speedup provided by the 10-stage pipeline? 5. If I was able to build a magical 1000-stage pipeline, where each stage took an equal amount of time, what speedup would I get? An unpipelined processor takes 10 ns to work on one instruction. It then takes 0.2 ns to latch its results into latches. I was able to convert the circuits into 10 sequential pipeline stages. The stages have the following lengths: 1.3ns; 0.7ns; 0.8ns; 1.2ns;0.7ns; 1.4ns; 0.7ns; 0.4ns; 1.5ns; 1.3ns. Answer the following questions, assuming that there are no stalls in the pipeline. 1. What is the clock speed in the unpipelined and pipelined processors (in MHz)? 2. What are the IPCs in the unpipelined and pipelined processors? 3. How long does it take to finish one instruction in the unpipelined and pipelined processors (in nano-seconds)? 4. What is the speedup provided by the 10-stage pipeline? 5. If I was able to build a magical 1000-stage pipeline, where each stage took an equal amount of time, what speedup would I get