2. The processor in Q1 above is converted into a 10-stage pipeline. The slowest of these 10 stages takes 250 ps, (including latch overheads). 1. What is the clock speed of this processor? (5 points) 2. What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache, and there are no stalls from data/control/structural hazards? (5 points) 3. What is the throughput of this processor (in billion instructions per second)? (10 points) 4. What is the speedup, relative to the unpipelined processor in Q1? Why is the speedup less than 10X? (10 points) 1. Consider an unpipelined or single-stage processor design like the one discussed in slide 4 of lecture 16. At the start of a cycle, a new instruction enters the processor and is processed completely within a single cycle. It takes 2,000 ps to navigate all the circuits in a cycle (including latch overheads). Therefore, for this design to work, the cycle time has to be at least 2,000 pice seconds. 1. What is the clock speed of this processor? (5 points) Clock Speed - cycle Time 2x 10-9 2. What is the CPI of this processor, assuming that every load/store -0.5 Gigahertz instruction finds its instruction/data in the instruction or data cache? (5 points) Cycles Per Instruction - 0.5 3. What is the throughput of this processor (in billion instructions per second)? (10 points) Throughput 2x10- 0.5 billion instructions per second