1. Consider an unpipelined or single-stage processor design like the one discussed in slide 3 of lecture 16. At the start of a cycle, a new instruction enters the processor and is processed completely within a single cycle. It takes 1,000 ps to navigate all the circuits in a cycle. Therefore, for this design to work, the cycle time has to be at least 1,000 pico seconds.

What is the clock speed of this processor? (5 points)

What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache? (10 points)

What is the throughput of this processor (in billion instructions per second)? (10 points)

2. The processor in Q1 above is converted into an 8-stage pipeline, similar to the one discussed on slide 8 of lecture 16. It takes 125 ps to navigate the circuits in each stage. Assume that latches do not introduce a noticeable delay overhead.

What is the clock speed of this processor? (5 points)

What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache, and there are no stalls from data/control/structural hazards? (10 points)

What is the throughput of this processor (in billion instructions per second)? (10 points)

3. Show how the following four consecutive instructions move through each stage of the five stage pipeline, similar to the example on slide 9 of lecture 17. This pipeline does not support any bypassing. Make sure the decode stage does not advance an instruction through the pipeline unless all data dependences are correctly resolved. (50 points) I1: add $s1, $s2, $s3 I2: lw $s4, 8($s2) I3: add $s5, $s4, $s1 I4: sw $s5, 8($s2)