Analyze the counter given by the following VHDL code.

Match each of the items that follow with its correct value.

ENTITY final$\_$exam$\_$VHDL$\_$counter IS

PORT

rstn$,$ clk : IN STD$\_$LOGIC;

count : OUT STD$\_$LOGIC$\_$VECTOR$(2$ DOWNTO $0))$;

END final$\_$exam$\_$VHDL$\_$counter ;

ARCHITECTURE behavioral OF final$\_$exam$\_$VHDL$\_$counter IS TYPE STATE$\_$TYPE IS $($A$,$B$,$C$,$D$,$E$,$F$,$G$,$H$)$;

SIGNAL state : STATE$\_$TYPE;

BEGIN

PROCESS

END PROCESS$$

Analyze the counter given by the following VHDL code.

Match each of the items that follow with its correct value.

ENTITY final$\_$exam$\_$VHDL$\_$counter IS

PORT $($

rstn$,$ clk : IN STD$\_$LOGIC;

count : OUT STD$\_$LOGIC$\_$VECTOR$(2$ DOWNTO $0))$;

END final$\_$exam$\_$VHDL$\_$counter ;

ARCHITECTURE behavioral OF final$\_$exam$\_$VHDL$\_$counter IS TYPE STATE$\_$TYPE IS $($A$,$ B$,$ C$,$ D$,$ E$,$ F$,$ G$,$ H$)$ ;

SIGNAL state : STATE$\_$TYPE;

BEGINWITH state SELECTcount OO$"$ WHEN D$,"001"$ WHEN A$,"010"$ WHEN G$,"011"$ WHEN E$,"100"$ WHEN H$,"101"$ WHEN B$,"110"$ WHEN F$,"111"$ WHEN C;

END behavioral;

Count sequence

Modulus

Number of unused states

Mealy or Moore machine $($clk$,$ rstn$)$

BEGIN