Answer with good high level explanation please

Recall that our MIPS $5-$stage scalar pipelined system includes $32$ general purpose

CPU registers and employs delayed branching. Suppose the system is modified to take

advantage of hyperthreading and includes control logic to alternately fetch an instruction

from three different threads to enter the pipeline.

a$)$ What is the minimum number of general purpose CPU registers required for the

modified system?

b$)$ Explain why each of the following units IS or IS NOT required with this modified

system:

a forwarding unit

a hazard detection unit

a branch prediction unit