Question: Design one of the following logic gates in static CMOS architecture using 50nm CMOS technology: 1. NAND3 2. NOR3 Simulate it. Use VDD as

Design one of the following logic gates in static CMOS architecture using

Design one of the following logic gates in static CMOS architecture using 50nm CMOS technology: 1. NAND3 2. NOR3 Simulate it. Use VDD as 1V. Please: 1. Take screenshots of the simulation. 2. Write the netlist. 3. Find the low-to-high and high-to-low and average propagation delays.

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