As you know, the MIPS processor described in this course employs a $5-$stage pipeline. The PC is incremented by $4$ in stage $1$ each time that an instruction is fetched. This incremented PC value is passed on to the following pipeline stages via the MIPS pipeline registers. When a MIPS beq instruction is in the execute stage the low $16$ bits in the instruction are shifted left $2$ bits and sign extended into an equivalent $32-$bit signed integer. This $32-$bit signed integer is added to the PC value from the ID$/$EX pipeline register and the sum is used as the branch target address for the MIPS beq instruction.

The ARM$7$ processor employs a $3-$stage pipeline $($fetch$,$ decode, execute$).$ The ARM$7$ execute stage effectively combines the activity performed in the MIPS execute, memory and write$-$back stages. ARM$7$ CPU register $15$ is used as the PC $($program counter$).$ This ARM$7$ PC register is incremented by $4$ in the fetch stage each time that an instruction is fetched. The ARM$7$ beq instruction, contains a signed integer in its low $24$ bits. This $24-$bit signed integer is shifted left two bits and signed extended to an equivalent $32-$bit signed integer. The $32-$bit signed integer is added to the ARM PC register and the sum is used as the branch target address for the ARM beq instruction.

Assume that the MIPS processor and the ARM$7$ processor must each execute a beq instruction that resides within its memory at address $0$x$400$B$5678.$ The branch target address for each beq instruction is $0$x$400$B$4000$