ASSIGNMENT$-4$: Design a Pulse with modulator $($PWM$)$ circuit that has a clock $($CLK$),$ reset $($RST$)$ and

$8-$bit Duty Cycle Input $($DCI$).$ It has also one$-$bit PWM output $($PWM$-$OUT$).$ It is requested to give $\%20,$

$\%50,$ and $\%80$ duty cycle output form your design.

Write down behavioral level SystemVerilog code of your design. Simulate your design with a testbench

SystemVerilog code. Synthesize your design. In your design use YOUR NAME and YOUR SURNAME as

module name.

NOTE THAT it must be conducted via System Verilog not Verilog