Assume a processor has CPIs $($clock cycles per instruction$)$ of $1\mathrm{.}3,6\mathrm{.}5,$ and $4\mathrm{.}5$ for arithmetic, load$/$store$,$ and branch instructions, respectively. On a single processor, assume a program requires $2\mathrm{.}56$E$9$ arithmetic instructions, $1\mathrm{.}28$E$9$ load$/$store instructions, and $256$ million branch instructions.

When the program is parallelized to run over multiple cores, the number of arithmetic and load$/$store instructions per processor is divided by $0\mathrm{.}78$ x p$,$ where p is the number of processors, but the number of branch instructions remains unchanged for each processor. Given a clock speed of $2$ GHz$,$ what is the speedup of $4$ processors over $1$ processor $($speedup is Execution time for $1$ processor $/$ execution time for N processors$)$