Question: Assume an address has 3 2 bits. A direct - mapped cache has 4 0 9 6 blocks, each containing 8 bytes. a . What

Assume an address has 32 bits. A direct-mapped cache has 4096 blocks, each containing 8 bytes. a. What is the width for the block offset? b. What is the bit width for cache index? c. What is the bit length of the tag? d. What is the size of a cache entry, including 1-bit valid bit?

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