Assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline (IF, ID, EX, MEM, WB), full data forwarding (including from MEM and WB stages to ID stage), hazard detection unit, and branch instruction is executed in ID stage. Assume that the first half of the clock cycle write-back stage writes to register file and the second half of the clock cycle the decode stage performs a read of source registers. Show a pipeline execution diagram for the program, where all data forwards are marked with arrows and stalls are marked with **. I1: lw $4, 8($16) I2: sub $5, $4, $1 I3: add $2, $4, $5